The junction field effect transistor (JFET) is a unipolar transistor that functions using only majority carriers. The JFET is a voltage-operated device.
JFETs are constructed from N-type and P-type semiconductor materials and are capable of amplifying electronic signals, but they are constructed differently from bipolar transistors and operate on different principles. Knowing how a JFET is constructed helps to understand how it operates.
Construction and Operation of JFET
Construction of JFET
Construction of JFET begins with a substrate, or base, of lightly doped semiconductor material. The substrate can be either P- or N-type material. The PN junction in the substrate is made using both the diffusion and growth methods. The shape of the PN junction is important.
Figure 1 shows a cross section of the embedded region within the substrate. The U-shaped region is called the channel and is flush with the upper surface of the substrate.
When the channel is made of N-type material in a P-type substrate, an N-channel JFET is formed. When the channel is made of P-type material in an N-type substrate, a P-channel JFET is formed.
Three electrical connections are made to a JFET (Figure 2). One lead is connected to the substrate to form the gate (G). One lead is connected to each end of the channel to form the source (S) and the drain (D).
It does not matter which lead is attached to the source or drain, because the channel is symmetrical.
Operation of JFET
The operation of JFET requires two external bias voltages. One of the voltage sources (EDS) is connected between the source and the drain, forcing the current to flow through the channel. The other voltage source (EGS) is connected between the gate and the source. It controls the amount of current flowing through the channel.
Figure 3 shows a properly biased N-channel JFET. Voltage source EDS is connected so that the source is made negative with respect to the drain. This causes a current to flow, because the majority carriers are electrons in the N-type material. The source-to-drain current is called the FET’s drain current (ID).
The channel serves as resistance to the supply voltage (EDS). The gate-to-source voltage (EGS) is connected so that the gate is negative with respect to the source.
This causes the PN junction formed by the gate and channel to be reverse biased. This creates a depletion region in the vicinity of the PN junction, which spreads inward along the length of the channel.
The depletion region is wider at the drain end because the EDS voltage adds to the EGS voltage, creating a higher-reverse bias voltage than that appearing across the source end.
The size of the depletion region is controlled by EGS. As EGS increases, so does the depletion region. A decrease in EGS causes a decrease in the depletion region.
When the depletion region increases, it effectively reduces the size of the channel. This reduces the amount of current that is able to flow through it. EGS can thus be used to control the drain current (ID) that flows through the channel.
An increase in EGS causes a decrease in ID. In normal operation, the input voltage is applied between the gate and the source. The resulting output current is the drain current (ID).
In a JFET, the input voltage is used to control the output current. In a transistor, it is the input current, not the voltage, that is used to control the output current.
Because the gate-to-source voltage is reverse biased, the JFET has an extremely high input resistance. If the gate-to-source voltage were forward biased, a large current would flow through the channel, causing the input resistance to drop and reducing the gain of the device.
The amount of gate-to-source voltage required to reduce ID to zero is called the gate-to-source cut-off voltage (EGS(off)). This value is specified by the manufacturer of the device.
The drain-to-source voltage (EDS) has control over the depletion region within the JFET. As EDS increases, ID also increases. A point is then reached where ID levels off, increasing only slightly as EDS continues to rise.
This occurs because the size of the depletion region has increased also, to the point where the channel is depleted of minority carriers and cannot allow ID to increase proportionally with EDS. The resistance of the channel also increases with an increase of EDS, with the result that ID increases at a slower rate.
However, ID levels off because the depletion region expands and reduces the channel’s width. When this occurs, ID is said to pinch off. The value of EDS required to pinch off or limit ID is called the pinch-off voltage (EP). EP is usually given by the manufacturer for an EGS of zero.
EP is always close to EGS(off) when EGS is equal to zero. When EP is equal to EGS the drain current is pinched off.
P-channel and N-channel JFETs have the same characteristics. The main difference between them is the direction of the drain current (ID) through the channel.
In a P-channel JFET, the polarity of the bias voltages (EGS, EDS) is opposite to that in an N-channel JFET.
The schematic symbols used for N-channel and P-channel JFETs are shown in Figure 4. The polarities required to bias an N-channel JFET are shown in Figure 5 and for a P-channel JFET in Figure 6.
Testing a field effect transistor is more complicated than testing a normal transistor. The following points must be considered prior to the actual testing of an FET.
- Is the device a JFET or a MOSFET?
- Is the FET an N-channel or a P-channel device?
- With MOSFETs, is the device an enhancement or a depletion mode device?
Before removing an FET from an circuit or handling it, check to see whether it is a JFET or a MOSFET. MOSFETs can be damaged easily unless certain precautions in handling are followed.
- Keep all of the leads of the MOSFET shorted until ready to use.
- Make sure the hand used to handle the MOSFET is grounded.
- Ensure that the power to the circuit is removed prior to insertion or removal of the MOSFET.
Both JFETs and MOSFETs can be tested using commercial transistor test equipment or an ohmmeter. If using commercial transistor test equipment, refer to the operations manual for proper switch settings.
Testing JFETs with Ohmmeter
1. Use a low-voltage ohmmeter in the R x 100 range.
2. Determine the polarity of the test leads. Red is positive and black is negative.
3. Determine the forward resistance as follows:
- N-channel JFETs: Connect the positive lead to the gate and the negative lead to the source or drain. Because the source and drain are connected by a channel, only one side needs to be tested. The forward resistance should be a low reading.
- P-channel JFETs: Connect the negative lead to the gate and the positive lead to the source or drain.
4. Determine the reverse resistance as follows:
- N-channel JFETs: Connect the negative test lead of the ohmmeter to the gate and the positive test lead to the source or drain. The JFET should indicate an infinite resistance. A lower reading indicates a short or leakage.
- P-channel JFETs: Connect the positive test lead of the ohmmeter to the gate and the negative test lead to the source or drain.
A JFET uses a channel instead of junctions (as in transistors) for controlling a signal. The three leads of a JFET are attached to the gate, source, and drain. The input signal is applied between the gate and the source for controlling a JFET.
JFETs have extremely high input resistance. The source and drain leads can be interchanged on most JFETs because the devices are symmetrical.
JFETs can be tested using a commercial transistor tester or an ohmmeter.