A power MOSFET is a metal oxide semiconductor field effect transistor. It is a three-terminal, voltage controlled majority carrier device and has a source lead (S), drain lead (D) and gate lead (G) similar to emitter, collector and base of a transistor, respectively.

The movement of the majority carriers in a MOSFET is controlled by the voltage applied on the gate which is insulated by a thin metal oxide layer from the bulk semiconductor body.

The flow of current between the two main current carrying terminals, the drain and the source is controlled by the voltage applied between the gate and source terminals.

Power MOSFETs are of two types: (a) depletion type and (b) enhancement type, similar to their integrated circuit counterparts.

Both of these can be either n-channel type or p-channel type depending on the nature of the bulk semiconductor or the substrate. The different symbols of the MOSFETS are shown in Fig. 1.

Construction of Power MOSFETs

Figures 2(a) and (b) show the schematic representation and the circuit symbol of an n-channel power MOSFET, respectively.

It consists of three layers, which are

1. an n-type semiconductor that is connected to the drain D;
2. an n-type semiconductor that is connected to source S and;
3. in between the source and the drain, there is a p-type semiconductor that is on the substrate.

The two n-type end layers are thus called the source and drain’ terminals and p-type middle layer is termed the body or substrate. The substrate is connected to the source within the MOSFET and gate is connected to a metallic conductor.

The gate is insulated from the semiconductor body be a thin layer of silicon dioxide which is also called as the gate oxide.

The source and the drain region of all cells on a wafer are connected to the same metallic contacts to form the source and the drain terminals of the complete device. All gate terminals are also connected together in a similar way.

The end n-type layers are heavily doped to almost the same level whereas the p-type substrate is moderately doped at level that is 2 – 3 times lower than that of end terminals.

The n− drain drift region above the n⁺ layer has the lowest doping density. Thickness of this region determines the actual breakdown voltage of the device.

The circuit symbol for p-type MOSFET is shown in Fig. 2(c).

Note that for the n-channel MOSFET, the arrow mark in the symbol points inward towards the gate and in case of p-channel MOSFET, the arrow mark points outwards, that is away from the gate.

The MOSFET cell with alternating n⁺ n⁻ p n⁺ structure embeds a parasitic NPN BJT between the drain and the source contacts with p-type substrate serving as its base. Its base and emitter are shorted by the source metallization into each MOSFET.

A non-zero resistance exists between the base and the emitter of the parasitic NPN BJT due to the body spreading resistance of the p-type substrate.

The MOSFET cells are to be designed in a manner that this resistance is minimized and switching operation of the parasitic BJT is suppressed.

To minimize the possibility that this transistor is ever turned ON, the p-type substrate is shorted to the source region. As a result, a parasitic diode, known as body diode exists between the drain and the source of the MOSFET.

The structural schematic of MOSFET in Fig. 2(a) suggests that there is no path for any current to flow between the source and the drain terminals because for any voltage (positive or negative) applied between the source and the drain terminals, at least one of the two p-n junctions, that is source-body or body-drain, will be reverse biased.

Also the current cannot be injected from the gate terminal due the presence of the gate oxide which is a good insulator.

However, when positive voltage is applied to the gate, an electric field is generated across the insulating silicon oxide layer which brings about polarization of charge within the oxide layer.

As a result these charges attract electrons from the p-type substrate thus creating an induced n-channel which bridges the n-type drain and source terminals.

Thus the source can be connected to the drain for conduction of current when positive drain voltage is applied.

Operation of Power MOSFETs

The MOSFET operations proceed through the following three stages:

1. Depletion layer formation: When a small positive voltage V_GS is applied between the gate and the source, the positive charge induced on the gate metal surface repels the majority hole carriers from the interface region between the gate oxide and the p-type body.

Thus, the negatively charged acceptors are exposed and a depletion region is created as shown in Fig. 3(a).

2. Free electron accumulation: Further increase in the applied voltage V_GS between gate and source causes the depletion layer to grow in thickness and the electric field at the oxide-silicon interface becomes large enough to attract free electrons, generated by thermal ionization of electron-holes as shown in Fig. 3(b).

Due to the increased V_GS, the holes are repelled into the semiconductor bulk ahead of the depletion region. The extra holes are neutralized by electrons from the source.

3. Inversion layer formation: When V_GS is further increased, the density of free electrons at the interface region becomes equal to the free hole density in the bulk of the body region beyond the depletion layer.

Thus an inversion layer is created, which acts as a n-type semiconductor and forms a conductive path between the drain and the source and permits flow of current between these two terminals as shown in Fig. 3(c).

Since the conduction of current in this device takes place through an n-type channel created by the electric field arising due to the voltage applied between the gate and source, it is called enhancement type n-channel MOSFET.

Static Characteristics of Power MOSFET

To obtain the static V-I characteristics, two voltage sources are to be connected to the MOSFET, one between drain and source with a series resistance and the other between gate and source also with a series resistance.

The source terminal is the common terminal between the input gate voltage and the drain-source voltage of the MOSFET. The magnitude of the applied gate to source voltage V_GS usually determines the drain current in a MOSFET.

The output characteristic of a power MOSFET is shown in Fig. 4, as the drain current (I_D) versus the drain-source voltage (V_DS), at different values of gate to source voltage (V_GS).

It can be seen from Fig. 4, that there is a threshold voltage, V_GS(th), below which the device is OFF and the MOSFET operates in the cut-off mode. This threshold voltage is of the order of 3—4 volts for most power MOSFETs.

When no drain current flows through the device the applied drain-source voltage (V_DS) is supported by the body-collector p-n junction of the device.

Therefore, in this situation, the maximum applied voltage V_DS between the drain and source should be below the avalanche breakdown voltage [V_DS(sat)] of this junction, to prevent destruction of the device.

In the active region, the drain current is independent of the drain-source voltage and depends only on V_GS, that is

I_D ∝ [V_GS – V_GS(th)]²

When the gate source voltage V_GS is increased beyond V_GS(th), the drain current starts flowing, even for small values of V_DS.

In the region where V_DS < (V_GS – V _GS(th)) the drain current I_D becomes almost proportional to V_DS and the region is called the ohmic region and the MOSFET is in ohmic mode of operation and can be treated an equivalent resistance in the circuit.

In power electronic applications, a MOSFET is operated as a switch where it is driven to either cut-off mode or to the ohmic mode.

The slope of the V_DS – I_D characteristics in the ohmic mode is called the equivalent ON state resistance of the MOSFET or R_DS(ON).

In order to reduce the power dissipation in the ON-state, the device should have low R_DS(ON) value. It is an important selection parameter for a device.

At still higher value of V_DS where V_DS > (V_GS – V _GS(th)), the I_D – V_DS characteristics deviates from the linear relationship of the ohmic region as shown in Fig. 4.

In this mode, for a given V_GS, I_D tends to saturate even with increase in V_DS