The 555 timer chip (such as the NE555 8-pin chip from Texas Instruments) is an integrated circuit that uses a transistor, resistors, flip-flops, comparators, and capacitors to produce a variety of clock signals, including a fixed pulse, a periodic signal, and a frequency dividing signal.
The NE555 can operate over a wide voltage supply range (5 to 15 VDC). With a 5 V supply, it has a TTL-compatible output that can sink or source up to 200 mA. The pin layout and a functional block diagram of the NE555 timer are shown in Figure 1.
The chip operation is controlled by the inputs applied to the trigger (TRIG) and threshold (THRES) pins. Each of these inputs is connected to a two-input comparator. The comparator outputs are attached to the set (S) and reset (R) inputs of the SR flip-flop.
The trigger and threshold inputs are irrelevant if the RESET input is low.
When the RESET input is high, the timer output changes according to the trigger and threshold levels. The functional operation is shown in following Table.
The trigger input sets the timer output to high if the trigger voltage level is below one-third of the supply voltage (VCC) regardless of the voltage level applied to the threshold input.
When the trigger voltage is larger than one-third of the supply voltage, the timer switches from high to low if the threshold voltage exceeds two-thirds of the supply voltage and maintains its output if the threshold voltage is below two-thirds of the supply voltage.
While the NE555 timer chip has several modes of operation, we will focus on two of them here. These are the monostable (or fixed-pulse generation) mode and the astable (or self-generating periodic signal) mode.
Monostable Operation of 555 Timer
In the monostable mode, the pulse properties are controlled by one external resistor and one capacitor. In the astable mode, two external resistors and one capacitor control the duty cycle and the frequency of the timing signal.
The wiring diagram for monostable operation is shown in Figure 2(a), and the timing diagram is shown in Figure 2(b). Here the output of the timer is controlled by the input signal applied to the trigger input.
- Initially, the internal SR flip-flop output is OFF, and the external capacitor C is held in the uncharged state by the internal transistor inside the timer.
- When a falling-edge pulse signal is applied to the trigger input with a voltage level less than one-third of the supply voltage, it causes the internal SR flip-flip to turn ON, and the timer output will be high.
This happens because the internal, lower-comparator output will be high, which will set the S input of the internal RS flip-flop to high.
- When the timer output turns high, the internal transistor is not conducting. This causes the capacitor C to charge through the resistor RA, since the DISCH pin is not connected to ground voltage in this case.
- When the voltage level at the capacitor C has reached two-thirds of the supply voltage, the internal flip-flop will reset, because the internal, upper-comparator output will be high and the internal lower comparator output will be low (provided that the trigger input has returned to high at this point). This causes the output of the timer to go low, and the voltage across the capacitor C will discharge through the internal transistor.
This cycle is repeated for every application of a falling-edge trigger pulse. The output pulse duration is approximately given by
TH = 1.1 RA C …..(equation 1)
Note that trigger signal duration has to be smaller than the output pulse duration. Otherwise, the timer output will remain high.
Astable Operation of 555 Timer
The wiring diagram for astable operation is given in Figure 3(a), and the timing diagram is shown in Figure 3(b).
A second resistor (RB) is added to the monostable circuit of Figure 2(a), and the threshold and trigger inputs are connected together causing the timer to self trigger.
In this configuration, the capacitor C charges through the resistors RA and RB, and discharges through RB only.
- When VCC is first turned on, the capacitor C is discharged, and the trigger input voltage level is zero. The timer output will be high.
- When the voltage across the capacitor reaches two-thirds of the supply voltage, the internal SR flip flop resets, the timer output switches to low, and the voltage across the capacitor C discharges through the internal transistor.
In the astable mode, the capacitor C alternates between charging and discharging states with the charging time is a function of the values of the resistors RA and RB and the capacitor C, and the discharging time is a function of the resistor RB and the capacitor C.
The on-time period (TH) and the off-time period (TL) are given by
TH = 0.693(RA + RB)C ….(equation 2)
TL = 0.693RBC ….(equation 3)
Component Selection for 555 Timer
Following example illustrates the selection of components for a 555 timer.
Example: Design a 555 timer circuit to produce a timing signal at a frequency of 1 kHz, and a duty cycle of 75%.
Solution: For 75% duty cycle, we obtain from Equations (2) and (3):
0.75 x 10-3 = 0.693(RA + RB)C
0.25 x 10-3 = 0.693 RBC
Dividing these equations, we obtain
3RB = RA + RB
Selecting C as 0.15 µF and solving, we obtain RB as 2405 Ω and RA as 4810 Ω. The 2.4 kΩ and the 4.8 kΩ are standard resistor values which can be used.