PLC Programming Languages
The term PLC programming language refers to the method by which the user communicates information to the PLC. The standard IEC 61131 ( Figure 1 ) was established to standardize the multiple languages associated with PLC programming by defining the following five standard languages:
- Ladder Diagram (LD): a graphical depiction of a process with rungs of logic, similar to the relay ladder logic schemes that were replaced by PLCs.
- Function Block Diagram (FBD): a graphical depiction of process flow using simple and complex interconnecting blocks.
- Sequential Function Chart (SFC): a graphical depiction of interconnecting steps, actions, and transitions.
- Instruction List (IL): a low-level, text-based language that uses mnemonic instructions.
- Structured Text (ST): a high-level, text-based language such as BASIC, C, or PASCAL specifically developed for industrial control applications.
Ladder diagram language is the most commonly used PLC language and is designed to mimic relay logic. The ladder diagram is popular for those who prefer to define control actions in terms of relay contacts and coils, and other functions as block instructions. Figure 2 shows a comparison of ladder diagram programming and instruction list programming. Figure 2a shows the original relay hardwired control circuit. Figure 2b shows the equivalent logic ladder diagram programmed into a controller.
Note how closely the ladder diagram program closely resembles the hardwired relay circuit. The input/output addressing is generally different for each PLC manufacturer. Figure 2c show how the original hardwired circuit could be programmed using the instruction list programming language. Note that the instructional list consists of a series of instructions that refer to the basic AND, OR, and NOT logic gate functions.
Functional block diagram programming uses instructions that are programmed as blocks wired together on screen to accomplish certain functions. Typical types of function blocks include logic, timers, and counters. Functional block diagrams are similar in layout to electrical/ electronic block diagrams used to simplify complex systems by showing blocks of functionality.
The primary concept behind a functional block diagram is data flow. Function blocks are linked together to complete a circuit that satisfies a control requirement. Data flow on a path from inputs, through function blocks or instructions, and then to outputs.
The use of function blocks for programming of programmable logic controllers (PLCs) is gaining wider acceptance. Rather than the classic contact and coil representation of ladder diagram or relay ladder logic programming, function blocks present a graphical image to the programmer with underlying algorithms already defined. The programmer simply completes needed information within the block to complete that phase of the program. Figure 3 shows function block diagram equivalents to ladder logic contacts.
Figure 4 illustrates how ladder diagram and functional block diagram programming could be used to produce the same logical output. For this application, the objective is to turn on caution pilot light PL 1 whenever both sensor switch 1 and sensor switch 2 are closed. The ladder logic consists of a single rung across the power rails. This rung contains the two input sensor instructions programmed in series with the pilot light output instruction.
The function block solution consists of a logic Boolean And function block with two input references tags for the sensors and a single output reference tag for the pilot light. Note there are no power rails in the function block diagram.
PLC Programming Languages
Sequential function chart programming language is similar to a flowchart of your process. SFC programming is designed to accommodate the programming of more advanced processes. This type of program can be split into steps with multiple operations happening in parallel branches. The basic elements of a sequential function chart program are shown in Figure 5 .
Structured text is a high level text language primarily used to implement complex procedures that cannot be easily expressed with graphical languages. Structured text uses statements to define what to execute. Figure 6 illustrates how structured text and ladder diagram programming could be used to produce the same logical output. For this application, the objective is to energize SOL 1 whenever either one of the two following circuit conditions exists:
- Sensor 1 and Sensor 2 switches are both closed.
- Sensor 3 and Sensor 4 switches are both closed and Sensor 5 switch is open.
The ladder diagram language is basically a symbolic set of instructions used to create the controller program. These ladder instruction symbols are arranged to obtain the desired control logic that is to be entered into the memory of the PLC. Because the instruction set is composed of contact symbols, ladder diagram language is also referred to as contact symbology.
Representations of contacts and coils are the basic symbols of the logic ladder diagram instruction set. The three fundamental symbols that are used to translate relay control logic to contact symbolic logic are Examine If Closed (XIC), Examine If Open (XIO), and Output Energize (OTE). Each of these instructions relates to a single bit of PLC memory that is specified by the instruction’s address. The symbol for the Examine If Closed (XIC) instruction is shown in Figure 7.
The XIC instruction, which is also called the Examine-on instruction, looks and operates like a normally open relay contact. Associated with each XIC instruction is a memory bit linked to the status of an input device or an internal logical condition in a rung. This instruction asks the PLC’s processor to examine if the contact is closed. It does this by examining the bit at the memory location specified by the address in the following manner:
- The memory bit is set to 1 or 0 depending on the status of the input (physical) device or internal (logical) relay address associated with that bit.
- A 1 corresponds to a true status or on condition.
- A 0 corresponds to a false status or off condition.
- When the Examine-on instruction is associated with a physical input, the instruction will be set to 1 when a physical input is present (voltage is applied to the input terminal), and 0 when there is no physical input present (no voltage applied to the input terminal).
- When the Examine-on instruction is associated by address with an internal relay, then the status of the bit is dependent on the logical status of the internal bit with the same address as the instruction.
- If the instruction memory bit is a 1 (true) this instruction will allow rung continuity through itself, like a closed relay contact.
- If the instruction memory bit is a 0 (false) this instruction will not allow rung continuity through itself and will assume a normally open state just like an open relay contact.
The symbol for the Examine If Open (XIO) instruction is shown in Figure 8 . The XIO instruction, which is also called the Examine-off instruction, looks and operates like a normally closed relay contact.
Associated with each XIO instruction is a memory bit linked to the status of an input device or an internal logical condition in a rung. This instruction asks the PLC’s processor to examine if the contact is open. It does this by examining the bit at the memory location specified by the address in the following manner:
- As with any other input the memory bit is set to 1 or 0 depending on the status of the input (physical) device or internal (logical) relay address associated with that bit.
- A 1 corresponds to a true status or on condition.
- A 0 corresponds to a false status or off condition.
- When the Examine-off instruction is used to examine a physical input, then the instruction will be interpreted as false when there is a physical input (voltage) present (the bit is 1) and will be interpreted as true when there is no physical input present (the bit is 0).
- If the Examine-off instruction were associated by address with an internal relay, then the status of the bit would be dependent on the logical status of the internal bit with the same address as the instruction.
- Like the Examine-on instruction, the status of the instruction (true or false) determines if the instruction will allow rung continuity through itself, like a closed relay contact.
- The memory bit always follows the status (true = 1 or false = 0) of the input address or internal address assigned to it. The interpretation of that bit, however, is determined by which instruction is used to examine it.
- Examine-on instructions always interpret a 1 status as true and a 0 status as false, while Examine-off instructions interpret a 1 status as false and a 0 status as true.
The symbol for the Output Energize (OTE) instruction is shown in Figure 9. The OTE instruction looks and operates like a relay coil and is associated with a memory bit. This instruction signals the PLC to energize (switch on) or de-energize (switch off ) the output.
The processor makes this instruction true (analogous to energizing a coil) when there is a logical path of true XIC and XIO instructions in the rung. The operation of the Output Energize instruction can be summarized as follows:
- The status bit of the addressed Output Energize instruction is set to 1 to energize the output and to 0 to de-energize the output.
- If a true logic path is established with the input instructions in the rung, the OTE instruction is energized and the output device wired to its terminal is energized.
- If a true logic path cannot be established or rung conditions go false, the OTE instruction is de-energized and the output device wired to it is switched off.
Sometimes beginner programmers used to thinking in terms of hardwired relay control circuits tend to use the same type of contact (NO or NC) in the ladder logic program that corresponds to the type of field switch wired to the discrete input. While this is true in many instances, it is not the best way to think of the concept.
A better approach is to separate the action of the field device from the action of the PLC bits as illustrated in Figure 10. A signal present makes the NO bit (1) true; a signal absent makes the NO bit (0) false. The reverse is true for an NC bit. A signal present makes the NC bit (1) false; a signal absent makes the NO bit (0) true.
The main function of the ladder logic diagram program is to control outputs based on input conditions, as illustrated in Figure 11. This control is accomplished through the use of what is referred to as a ladder rung. In general, a rung consists of a set of input conditions, represented by contact instructions, and an output instruction at the end of the rung, represented by the coil symbol.
Each contact or coil symbol is referenced with an address that identifies what is being evaluated and what is being controlled. The same contact instruction can be used throughout the program whenever that condition needs to be evaluated. The number of ladder logic relays and input and output instructions is limited only by memory size. Most PLCs allow more than one output per rung.
For an output to be activated or energized, at least one left-to-right true logical path must exist, as illustrated in Figure 12.
A complete closed path is referred to as having logical continuity. When logical continuity exists in at least one path, the rung condition and Output Energize instruction are said to be true. The rung condition and OTE instruction are false if no logical continuity path has been established. During controller operation, the processor evaluates the rung logic and changes the state of the outputs according to the logical continuity of rungs.
To complete the entry of a relay-type instruction, you must assign an address to each instruction. This address indicates what PLC input is connected to what input device and what PLC output will drive what output device.
The addressing of real inputs and outputs, as well as internals, depends on the PLC model used. Addressing formats can vary from one PLC family to another as well as for different manufacturers. These addresses can be represented in decimal, octal, or hexadecimal depending on the number system used by the PLC. The address identifies the function of an instruction and links it to a particular bit in the data table portion of the memory.
Figure 13 shows the addressing format for an AllenBradley SLC 500 controller. Addresses contain the slot number of the module where input or output devices are connected. Addresses are formatted as file type, slot number, and bit. The assignment of an I/O address can be included in the I/O connection diagram, as shown in Figure 14. Inputs and outputs are typically represented by squares and diamonds, respectively.
Branch instructions are used to create parallel paths of input condition instructions. This allows more than one combination of input conditions (OR logic) to establish logic continuity in a rung. Figure 15 illustrates a typical branch instruction. The rung will be true if either instruction A or B is true. Input branching by formation of parallel branches can be used in your application program to allow more than one combination of input conditions.
If at least one of these parallel branches forms a true logic path, the rung logic is true and the output will be energized. If none of the parallel branches complete a logical path, logic rung continuity is not established and the output will not be de-energized.
In the example shown in Figure 16, either A and B, or C provides logical continuity and energizes output D. On most PLC models, branches can be established at both input and output portions of a rung. With output branching, you can program parallel outputs on a rung to allow a true logic path to control multiple outputs, as illustrated in Figur 17.
When there is a true logic rung path, all parallel outputs become true. In the example shown, either A or B provides a true logical path to all three output instructions: C, D, and E.
Additional input logic instructions (conditions) can be programmed in the output branches to enhance conditional control of the outputs. When there is a true logic path, including extra input conditions on an output branch, that branch becomes true.
In the example shown in Figure 18, either A and D or B and D provide a true logic path to E. Input and output branches can be nested to avoid redundant instructions and to speed up processor scan time.
Figure 19 illustrates nested input and output branches. A nested branch starts or ends within another branch. In some PLC models, the programming of a branch circuit within a branch circuit or a nested branch cannot be done directly. It is possible, however, to program a logically equivalent branching condition.
Figure 20 shows an example of a circuit that contains a nested contact D. To obtain the required logic, the circuit would be programmed as shown in Figure 21. The duplication of contact C eliminates the nested contact D. Nested branching can be converted into nonnested branches by repeating instructions to make parallel equivalents.
Some PLC manufacturers have virtually no limitations on allowable series elements, parallel branches, or outputs. For others, there may be limitations to the number of series contact instructions that can be included in one rung of a ladder diagram as well as limitations to the number of parallel branches.
Also, there is an additional limitation with some PLCs: only one output per rung and the output must be located at the end of the rung. The only limitation on the number of rungs is memory size. Figure 22 shows the matrix limitation diagram for a typical PLC. A maximum of seven parallel lines and 10 series contacts per rung is possible.
Another limitation to branch circuit programming is that the PLC will not allow for programming of vertical contacts. A typical example of this limitation is contact C of the user program drawn in Figure 23. To obtain the required logic, the circuit would be reprogrammed as shown in Figure 24 .
The processor examines the ladder logic rung for logic continuity from left to right only. The processor never allows for flow from right to left. This situation presents a problem for user program circuits similar to that shown in Figure 25 .
If programmed as shown, contact combination FDBC would be ignored. To obtain the required logic, the circuit would be reprogrammed as shown in Figure 26.
Internal Relay Instructions
Most PLCs have an area of the memory allocated for what are known as internal storage bits. These storage bits are also called internal outputs, internal coils, internal control relays, or simply internal bits. Internal outputs are on/ off signals generated by programmed logic.
Unlike a discrete output, an internal output does not directly control an output field device. The internal output operates just like any output that is controlled by programmed logic; however, the output is used strictly for internal purposes. The advantage of using internal outputs is that there are many situations in which an output instruction is required in a program but no physical connection to a field device is needed.
If there are no physical outputs wired to a bit address, the address can be used as an internal storage point. Internal storage bits or points can be programmed by the user to perform relay functions without occupying a physical output. In this way internal outputs can minimize output module point requirements whenever practical.
Internal outputs are single-bit storage locations in memory and are addressed as such. SLC 500 controllers use bit file B3 for storage and addressing of internal output bits.
The addressing for bit B3:1/3 illustrated in Figure 27 consists of the file number followed by word and bit numbers. An internal control relay can be used when a program requires more series contacts than the rung allows. Figure 28 shows a circuit that allows for only 7 series contacts when 12 are actually required for the programmed logic.
To solve this problem, the contacts are split into two rungs. Rung 1 contains seven of the required contacts and is programmed to control internal relay coil B3:1/3. The address of the first programmed contact on Rung 2 is B3:1/3 followed by the remaining five contacts and the discrete output.
When the logic controlling the internal output is true, the referenced bit B3:1/3 is turned on or set to 1. The advantage of an internal storage bit in this manner is that it does not waste space in a physical output.
Programming Examine If Closed and Examine If Open Instructions
A simple program using the Examine If Closed (XIC) instruction is shown in Figure 29. This figure shows a hardwired circuit and a user program that provides the same results.
You will note that both the NO and the NC pushbuttons are represented by the Examine If Closed symbol. This is because the normal state of an input (NO or NC) does not matter to the controller. What does matter is that if contacts need to close to energize the output, then the Examine If Closed instruction is used.
Since both PB1 and PB2 must be closed to energize the pilot light, the Examine If Closed instruction is used for both. A simple program using the Examine If Open (XIO) instruction is shown in Figure 30.
Both the hardwired circuit and user program are shown. In the hardwired circuit, when the pushbutton is open relay coil CR is de-energized and its NO contact closes to switch the pilot light on. When the pushbutton is closed, relay coil CR is energized and its NC contact opens to switch the pilot light off. The pushbutton is represented in the user program by an Examine If Open instruction. This is because the rung must be true when the external pushbutton is open and false when the pushbutton is closed.
Using an Examine If Open instruction to represent the pushbutton satisfies these requirements. The NO or NC mechanical action of the pushbutton is not a consideration. It is important to remember that the user program is not an electrical circuit but a logic circuit. In effect, we are interested in logic continuity when establishing an output.
Figure 31 shows a simple program using both the XIC and XIO instructions. The logic states (0 or 1) indicate whether an instruction is true or false and is the basis of controller operation. The figure summarizes the on/off state of the output as determined by the changing states of the inputs in the rung. The time aspect relates to the repeated scans of the program, wherein the input table is updated with the most current status bits.
- Introduction to Programmable Logic Controllers
- Parts of Programmable Logic Controller
- Input Output Section of PLC
- Discrete I/O Modules of PLC
- Analog I/O Modules of PLC
- I/O Module Specifications of PLC
- Central Processing Unit of PLC
- Boolean Equation for Logic Gate Circuits
- Memory Map for PLC Processor
- PLC Program Scan Cycle
- PLC Programming Languages
- Entering Ladder Diagram
- PLC Ladder Logic Programs
- Timer Instructions in PLC
- Counter Instructions in PLC
- Control Instructions in PLC
- Data Manipulation Instructions in PLC
- PLC Math Instructions
- PLC Sequencer Instructions & Programs
- PLC Shift Register Instructions & Programs
- Installation and Commissioning of PLC
- Troubleshooting of PLC
- Process Control Systems
- PLC Data Communication System