Interfacing of Logic Families

Interfacing of Logic Families

CMOS and TTL are the two most widely used logic families. Although ICs belonging to the same logic family have no special interface requirements, that is, the output of one can directly feed the input of the other, the same is not true if we have to interconnect digital ICs belonging to different logic families.

Incompatibility of ICs belonging to different families mainly arises from different voltage levels and current requirements associated with LOW and HIGH logic states at the inputs and outputs.

In this article, we will discuss simple interface techniques that can be used for CMOS-to-TTL and TTL-to-CMOS interconnections. Interface guidelines for CMOS–ECL, ECL–CMOS, TTL–ECL and ECL–TTL are also given.

CMOS-to-TTL Interface

The first possible type of CMOS-to-TTL interface is the one where both ICs are operated from a common supply. We know that the TTL family has a recommended supply voltage of 5 V, whereas the CMOS family devices can operate over a wide supply voltage range of 3–18 V.

In the present case, both ICs would operate from 5 V. As far as the voltage levels in the two logic states are concerned, the two have become compatible.

The CMOS output has a VOH(min.) of 4.95 V (for VCC = 5 V) and a VOL(max.) of 0.05 V, which is compatible with VIH(min.) and VIL(max.) requirements of approximately 2 and 0.8 V respectively for TTL family devices.

In fact, in a CMOS-toTTL interface, with the two devices operating on the same VCC, voltage level compatibility is always there. It is the current level compatibility that needs attention.

That is, in the LOW state, the output current-sinking capability of the CMOS IC in question must at least equal the input current-sinking requirement of the TTL IC being driven.

Similarly, in the HIGH state, the HIGH output current drive capability of the CMOS IC must equal or exceed the HIGH-level input current requirement of TTL IC. For a proper interface, both the above conditions must be met.

As a rule of thumb, a CMOS IC belonging to the 4000B family (the most widely used CMOS family) can feed one LS TTL or two low-power TTL unit loads.

When a CMOS IC needs to drive a standard TTL or a Schottky TTL device, a CMOS buffer (4049B or 4050B) is used. 4049B and 4050B are hex buffers of inverting and noninverting types respectively, with each buffer capable of driving two standard TTL loads.

interfacing of logic families
Fig. 1(a)

Figure 1(a) shows a CMOS-to-TTL interface with both devices operating from 5 V supply and the CMOS IC driving a low-power TTL or a low-power Schottky TTL device.

Fig. 1(b)

Figure 1(b) shows a CMOS-to-TTL interface where the TTL device in use is either a standard TTL or a Schottky TTL.

interfacing of logic families
Fig. 1(c)

The CMOS-to-TTL interface when the two are operating on different power supply voltages can be achieved in several ways. One such scheme is shown in Fig. 1(c). In this case, there is both a voltage level as well as a current level compatibility problem.

TTL-to-CMOS Interface

In the TTL-to-CMOS interface, current compatibility is always there. The voltage level compatibility in the two states is a problem. VOH (min.) of TTL devices is too low as regards the VIH (min.) requirement of CMOS devices.

Fig. 2(a)

When the two devices are operating on the same power supply voltage, that is, 5 V, a pull-up resistor of 10 kΩ achieves compatibility [Fig. 2(a)]. The pull-up resistor causes the TTL output to rise to about 5 V when HIGH.

Fig. 2(b)
Fig. 2(c)

When the two are operating on different power supplies, one of the simplest interface techniques is to use a transistor (as a switch) in-between the two, as shown in Fig. 2(b). Another technique is to use an open collector type TTL buffer [Fig. 2(c)].

TTL-to-ECL and ECL-to-TTL Interfaces

TTL-to-ECL and ECL-to-TTL interface connections are not as straightforward as TTL-to-CMOS and CMOS-to-TTL connections owing to widely different power supply requirements for the two types and also because ECL devices have differential inputs and differential outputs.

Nevertheless, special chips are available that can take care of all these aspects. These are known as level translators. MC10124 is one such quad TTL-to-ECL level translator. That is, there are four independent single-input and complementary-output translators inside the chip.

Fig. 3(a)

Figure 3(a) shows a TTL-to-ECL interface using MC10124. MC10125 is a level translator for ECL-to-TTL interfaces; it has differential inputs and a single-ended output.

Fig. 3(b)

Figure 3(b) shows a typical interface schematic using MC10125. Note that in the interface schematics of Figs 3(a) and (b), only one of the available four translators has been used.

CMOS-to-ECL and ECL-to-CMOS Interfaces

CMOS-to-ECL and ECL-to-CMOS interfaces are similar to the TTL-to-ECL and ECL-to-TTL interfaces described. Again, dedicated level translators are available. MC10352, for instance, is a quad CMOS-to-ECL level translator chip. A CMOS-to-ECL interface is also possible by having firstly a CMOS-to-TTL interface followed by a TTL-to-ECL interface using MC10124 or a similar chip.

Fig. 4(a)
Fig. 4(b)

Figure 4(a) shows the arrangement. Similarly, an ECL-to-CMOS interface is possible by having an ECL-to-TTL interface using MC10125 or a similar chip followed by a TTL-to-CMOS interface. Figure 4(b) shows a typical interface schematic.

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  7. Interfacing of Logic Families
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