# Function of Adder, Subtractor & Comparator

An adder is the primary computation unit in a digital computer. Few routines are performed by a computer in which the adder is not used. Adders are designed to work in either serial or parallel circuits.

Because the parallel adder is faster and used more often, it is covered in more detail here. To understand how an adder works it is necessary to review the rules for adding:

Figure 1 shows a truth table based on these rules. Note that the Greek letter sigma (∑) is used to represent the sum column. The carry column is represented by C0. These terms are used by industry when referring to an adder.

The sum column of the truth table is the same as the output column in the truth table of an exclusive OR gate (Figure 2). The carry column is the same as the output in a truth table for an AND gate (Figure 3).

Figure 4 shows an AND gate and an exclusive OR gate connected in parallel to provide the necessary logic function for single-bit addition. The carry output (C0) is produced with the AND gate, and the sum output (∑) is produced with the XOR gate.

The inputs A and B are connected to both the AND gate and the XOR gate. The truth table for the circuit is the same as the truth table developed using the binary addition rules (Figure 1). Because the circuit does not take into account any carries, it is referred to as a half adder. It can be used as the LSB adder for a binary addition problem.

An adder that takes into account the carry is called a full adder. A full adder accepts three inputs and generates a sum and carry output.

Figure 5 shows the truth table for a full adder. The C1 input represents the carry input. The C0 output represents the carry output.

Figure 6 shows a full adder constructed of two half adders. The results of the first half adder are “OR”ed with the second half adder to form the carry output. The carry output is a 1 if both inputs to the first XOR gate are 1’s or if both inputs to the second XOR gate are 1’s.

Figure 8 shows the symbols used to represent a half adder and a full adder. A single full adder is capable of adding two single-bit numbers and an input carry. To add binary numbers with more than 1-bit, additional full adders must be used.

Remember, when one binary number is added to another, each column that is added generates a sum and a carry of 1 or 0 to the next higher-order column.

To add two binary numbers, a full adder is required for each column. For example, to add a 2-bit number to another 2-bit number, two adders are required. Two 3-bit numbers require three adders, two 4-bit numbers require four adders, and so on.

The carry generated by each adder is applied to the input of the next higher-order adder. Because no carry input is required for the least significant position, a half adder is used.

Figure 9 shows a 4-bit parallel adder. The least significant input bits are represented by A0 and B0. The next higher-order bits are represented by A1 and B1 and so on. The output sum bits are identified as ∑0,∑1,∑2 and so on. Note that the carry output of each adder is connected to the carry input of the next higher-order adder. The carry output of the final adder is the most significant bit of the answer.

## Function of Subtractor

A subtractor allows subtraction of two binary numbers. To understand how a subtractor works it is necessary to review the rules for subtraction.

Figure 10 shows a truth table based on these rules. The letter D represents the difference column. The borrow column is represented by B0.

Notice that the difference output (D) is 1 only when the input variables are not equal. Therefore, the difference can be expressed as the exclusive OR of the input variables. The output borrow is generated only when A is 0 and B is 1. Therefore, the borrow output is the complement of A “AND”ed with B.

Figure 11 shows a logic diagram of a half subtractor. It has two inputs and generates a difference and a borrow output. The difference is generated by an XOR gate and the borrow output is generated by an AND gate with A and B inputs. The A is achieved by using an inverter on the variable A input.

However, a half subtractor is identified as such because it does not have a borrow input. A full subtractor does. It has three inputs and generates a difference and a borrow output. A logic diagram and truth table for a full subtractor are shown in Figure 12.

Figure 13 shows the symbols used to represent a half subtractor and full subtractor.

A full subtractor can handle only two 1-bit numbers. To subtract binary numbers with more than 1 bit, additional full subtractors must be used. Keep in mind that if a 1 is subtracted from a 0, a borrow must be made from the next higher-order column. The output borrow of the lower-order subtractor becomes the input borrow of the next higher-order subtractor.

Figure 14 shows a block diagram of a 4- bit subtractor. A half subtractor is used in the least significant bit position because there is no input borrow.

## Function of Comparator

A comparator is used to compare the magnitudes of two binary numbers. It is a circuit used simply to determine if two numbers are equal. The output not only compares two binary numbers but also indicates whether one is larger or smaller than the other.

Figure 15 shows a truth table for a comparator. The only time an output is desired is when both bits being compared are the same. The output column represents an exclusive OR with an inverter, also known as an exclusive NOR (XNOR) gate. An XNOR gate is essentially a comparator, because its output is a 1 only if the two inputs are the same. To compare numbers containing 2 bits or more, additional XNOR gates are necessary.

Figure 16 shows a logic diagram of a comparator for checking two 2-bit numbers. If the numbers are equal, a 1 is generated from the XNOR gate. The 1 is applied to the AND gate as a qualifying level.

If both XNOR gates produce a 1 for the inputs to the AND gate, that identifies the numbers as equal and generates a 1 for the output of the AND gate. However, if the inputs to the XNOR gate are different, the XNOR gate generates a 0, which disqualifies the AND gate. The output of the AND gate is then a 0.

Figure 17 shows a logic diagram of a comparator for checking two 4-bit numbers. Figure 18 is the diagram used to represent a 4-bit comparator.

## Summary

• The truth table for the adding rules of binary numbers is equivalent to the truth table for an AND gate and an XOR gate.
• A half adder does not take into account the carry.
• A full adder takes the carry into account.