Digital circuits are commonly available in two families: transistor-transistor logic (TTL) and complementary metal-oxide semiconductor (CMOS). There are other families, such as emitter-coupled logic (ECL), but they are not as widely used.
TTL devices are based on the bipolar junction transistor technology, while CMOS devices are based on the FET transistor technology. Table 1 shows the voltage levels for the two families for a 5 V supply. The values define the allowable voltage ranges for the low and high logic states.
Note how the output level range for either logic state is smaller than the corresponding input level range for that state. This is to allow for noise and signal variation in the output voltage values.
Digital Circuit Families
Table 2 compares the two families in several categories. In general, CMOS ICs consume less power than TTL ICs and can operate over a wider voltage supply range, but they can be easily damaged by static electricity, and proper grounding is needed when handling CMOS ICs.
|Supply Voltage||Tight supply voltage (about 4.50 to|
|Can operate over a wide supply|
range from 3 to 18 V
|Power Consumption||High but power consumption does|
not increase with signal frequency
|Much lower power consumption|
than TTL, but power consumption increases with frequency
|Static Sensitivity||Not sensitive||Very sensitive|
|Unused Inputs||Can be left floating||Should be tied to ground or to +V|
|Operating Frequency||Higher than CMOS||Lower than TTL due to MOSFET|
|Gate Propagation Time||∼10 ns||Slower than TTL (Advanced CMOS logic features gate delays of less than 0.1 ns)|
|Input Current||High current draw||Very low current draw at gate input|
|Output Current||Source about 2 mA but can sink|
about 16 mA
|Can sink or source about 4 mA|
|Fan-out||One output can drive about 10 inputs||One output can drive about 50 inputs|
In Table 2, gate propagation delay refers to the time it takes for a gate to switch logic levels from either high to low or from low to high. The propagation delay time from low to high (tPLH) and from high to low (tPHL) are generally not the same, and the largest of the two is used.
Fan out refers to the number of inputs that can be driven by one output. CMOS devices have a higher fan out than TTL devices.
The terms current sinking and sourcing are commonly used when listing specifications about IC. A device is said to be sinking current if the current flows into the output gate of the IC device when the output is low, while a device is said to be sourcing current if the current flows from the output gate of the IC device when the output is high. As listed in Table 2, TTL devices can sink much more current than CMOS devices.
Within each family, there are several sub-families or series of ICs. The different subfamilies are listed in Table 3, 4 along with some information about each sub-family. This table is not comprehensive, as there exist over 30 sub-families.
|Regular TTL||—||7408||Original TTL series. Has high|
|L||74L08||Lower power than regular|
TTL but also lower speed
|H||74H08||Double the speed and power|
of the regular TTL series
|Schottky TTL||S||74H08||Uses more power than|
regular TTL but is faster
|LS||74LS08||Lower power version of|
|AS||74AS08||Faster than S series with|
lower input current
|ALS||74ALS08||Very low power dissipation|
|Fast TTL||F||74F08||Lower power than S and|
|Metal Gate||C||74C08||Pin-compatible with TTL||Can use 3 to 15 V|
|HC||74HC08||Pin-compatible with TTL|
and has same speed as the
|Requires 2 to 6 V|
power supply. Can
drive 74LS devices
but not driven by
|HCT||74HCT08||Pin compatible with TTL||Requires 5 ± 0.5 V|
supply. Can be
74LS devices for
both input and
|ACT||74ACT08||Inputs are TTL-voltage|
|Requires 5 ± 0.5 V|
Most TTL and CMOS devices are designated using the notation:
where mm is a 2- or 3-letter code for the manufacturer (such as DM for National Semiconductor and SN for Texas Instruments)
NN is either 74 or 54 and refers to operating temperature range, where 74 is for industrial applications (0 to 70°C), and 54 is for military applications (-55 to 125°C).
ss refers to the sub-family (such as LS for low-power Schottky) dd is a 2- to 4-digit device number (such as 08 for an AND gate)
p is the designation for the type of package in which the device is available (such as N for plastic DIP)
For example, the SN74LS08N is a TTL AND gate of the low-power Schottky series designed for commercial applications and manufactured by Texas Instruments in the DIP plastic package type.
Note that TTL and CMOS devices have been in existence for many years, and several of the sub-families listed in Table 3 are now obsolete but are mentioned for reference.
In data sheets for TTL and CMOS devices, several parameters are defined:
VCC Supply voltage
VOL Output voltage when the output is LOW
VOH Output voltage when the output is HIGH
VIL Input voltage when the input is LOW
VIH Input voltage when the input is HIGH
IOL Output current when the output is LOW
IOH Output current when the output is HIGH
IIL Input current when the input is LOW
IIH Input current when the input is HIGH
As an example, Table 5 lists the values of these parameters for the SN74LS08 and the SN74HCT08 AND gates.
Note that for current, the convention is that the current entering a device (sinking) is positive, and a current leaving a device (sourcing) is negative.
By examining the values of the input and output currents at low and high logic states, one can determine how many inputs can be connected to the output of one gate or fan out. For example, for the TLL AND gate in Table 5, one output can drive up to 20 TTL AND inputs (IOL/IIL = 8 mA/0.4 mA = 20).
Table 5 shows that for the CMOS AND gate, the input current is significantly smaller than that for the TTL gate.
Types of TTL Output
TTL devices are available with different types of outputs. These include totem-pole, open-collector, and tristate.
Totem-pole is the most commonly used construction. The output gate has two transistors stacked on the top of each other, as seen in Figure 1 and, hence, the name totem pole.
When the output is high, transistor Q4 is ON and transistor Q3 is OFF. In this case, current flows through Q4 and out of the device. Thus, when the output is high, the gate is sourcing current, and IOH is negative.
When the output is low, transistor Q4 is off, and transistor Q3 is on. Current flows into the output gate through transistor Q3. Thus, the output gate is sinking current, and in this case, IOL is positive.
In open-collector configuration, an external ‘pull-up’ resistor needs to be connected to the output gate. This situation is similar to the totem-pole configuration of Figure 1 with transistor Q4 not present Fig. 2.
Figure 3 shows a typical wiring of an open-collector AND gate. When the transistor Q3 is ON, the output voltage of the gate will be at a low logic level or close to 0 V (about 0.2 V). When transistor Q3 is OFF, the output voltage of the gate will be pulled to the supplied voltage (VS).
Note that with open-collector output, the high logicstate voltage output is not limited to the IC VCC voltage but could be any voltage higher or lower than VCC.
An example of open collector AND gate is the DM74LS09 IC.
ICs with open-collector output are typically used to interface ICs from different logic families (such as TTL and CMOS).
In tristate output, the gate has an additional input called enable. When the enable input is low, the output can be either low or high, depending on the input applied to the gate.
When the enable input is high, the output is disconnected from the rest of the circuit. The gate will have a high output impedance in this state.
Three-state output is used in cases where data from several digital devices is transferred on a common line or bus. The enable signal is then used to connect/ disconnect these devices from the bus. Examples of such devices include buffers, flip-flops, and memory chips.
Interfacing Devices from Different Families
The question that arises is whether devices from different families can be interfaced together. The answer depends on the sub-family of the device. In general, most TLL and CMOS sub-families cannot be directly interfaced due to voltage level incompatibility, but the CMOS 74HCT and the TTL 74LS sub-families can be mixed together without using any additional components.
For interfacing a TTL output to a CMOS input where there is a voltage incompatibility, a pull-up resistor is added to the output of a TTL device before it is interfaced with the CMOS device.
This insures that the high-output voltage of the TTL device (VOH) is higher than the high-input voltage (VIH) of the CMOS device. The pull-up resistor resistance value should be selected such that the IOL for the TTL device is not exceeded.
A CMOS device from the HC or HCT series can drive a single LS device. For driving multiple LS devices, a buffer is inserted between the CMOS output and the TTL inputs to meet the current requirements.